You might begin to wonder how long we can keep increasing our computing capacity, because for more than 50 years, computer processors have increased in power and shrunk in size at a tremendous rate. We do know that today’s chip designers are hitting physical limitations, and so this is halting the pace of product innovation from scaling alone. With virtually all electronic equipment today built on complementary-symmetry metal-oxide-semiconductor (CMOS) technology, where do we go next?
Well, apparently IBM has an answer (is this why warren Buffet bought so much stock?). IBM scientists have unveiled three exploratory research breakthroughs that could lead to major advancements in delivering dramatically smaller, faster and more powerful computer chips: a CMOS-compatible graphene device, a carbon nanotube device, and the first Racetrack memory device integrated with CMOS technology on 200mm wafers. Lets take a quick look at each.
CMOS-compatible graphene device
First up is the first-ever CMOS-compatible graphene device, which can advance wireless communications, and enable new, high frequency devices that can operate under adverse temperature and radiation conditions in areas such as security and medical applications. The graphene integrated circuit, a frequency multiplier, is operational up to 5 GHz and stable up to 200 degrees Celsius.
This new architecture flips the current graphene transistor structure on its head. Instead of trying to deposit gate dielectric on an inert graphene surface, the researchers developed a novel embedded gate structure that enables high device yield on a 200mm wafer.
A carbon nanotube device
Next we have the first transistor with sub-10 nm channel lengths, a carbon nanotube device, outperforming the best competing silicon-based devices at these length scales.
It is expected that computers with in the next decade will use transistors with a channel length below 10 nm, a length scale at which conventional silicon technology will have extreme difficulty performing, even with new advanced device architectures. The devices below 10nm gate length are a significant breakthrough for future applications in computing technology. This breakthrough demonstrates for the first time that carbon nanotubes can provide excellent off-state behavior in extremely scaled devices, (that’s what IBM claims).
Finally we have the first Racetrack memory device integrated with CMOS technology on 200mm wafers, culminating seven years of physics research. Racetrack memory combines the benefits of magnetic hard drives and solid-state memory to overcome challenges of growing memory demands and shrinking devices.
The researchers demonstrated both read and write functionality on an array of 256 in-plane, magnetized horizontal racetracks. This development lays the foundation for further improving Racetrack memory’s density and reliability using perpendicular magnetized racetracks and three-dimensional architectures. This breakthrough could lead to a new type of data-centric computing that allows massive amounts of stored information to be accessed in less than a billionth of a second (yep, another IBM claim).
All in all, its cool stuff, and so we are clearly not yet at the end of the road.